Slave clock

With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).

从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。

It is shown by theory and case study that the master - slave clock mode in a com munication system is ideal for proper functions of the current differential protection.

理论及实例分析表明，通信系统的主—从时钟方式是电流差动保护装置在复用数字通信系统时正确工作的理想方式。

The micro-processor and VLSIC are core of the master clock, which consists of a control unit and can adjust all slave clocks (except standard time slave clock) clockwise and inversion quickly.

器件为核心，构成一控制单元，操作非常简单，且可以同时对所有子钟进行顺时针和逆时针快速调整，运行可靠。