Digital Circuits and Logic Design

This dissertation focuses on the high performance digital circuits design and relative issues, using the concept of logic balance.

本文结合工程背景，运用逻辑平衡的思想对高速数字电路的设计及相关问题进行了全面的研究。

This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.

本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。

In system digital part design, all outer logic circuits of Single chip microcomputer are implemented in CPLD. That makes the volume of the system smaller and improve the reliability of system.

在系统数字部分的设计中，采用CPLD来实现单片机外部的逻辑电路，大大缩小了整个系统的体积提高了系统的可靠性。